1. Field of the Invention
The present invention relates, in general, to a semiconductor device and, more particularly, to a semiconductor device such as a dynamic random access memory (DRAM) including a transistor having an elevated source/drain (ESD) structure in at least a peripheral circuit region.
2. Description of the Related Art
In a semiconductor device, two or more transistors with different characteristics are often mounted on a single substrate.
For example, a semiconductor device such as a DRAM includes, on a semiconductor substrate, a cell transistor connected to a memory device such as a capacitor, a transistor of an array circuit such as X and Y decoders for control of a memory cell, a transistor of a peripheral circuit for control of data I/O or an array circuit. Generally, from the viewpoint of providing a prescribed area of a memory cell region with cells as many as possible, transistors are closely packed rather than those of the array circuit and peripheral circuit.
Conventionally, it is general that the transistors of the array circuit and peripheral circuit (hereinafter such a transistor is referred to as a ‘peripheral circuit transistor’, and the region where the ‘peripheral circuit transistors’ are mounted is referred to as a ‘peripheral circuit region’), which are required to operate at high speed, form a high density impurity diffusion layer so as to make source/drain have low resistance. In case of forming high density impurity diffusion layer, a problem of short channel effect is caused due to diffusion of impurities towards a channel. To solve this problem, it is proposed that an LDD structure or an extension region is provided. With advance of generation in development of a semiconductor device, there is a need that source/drain region has to be made shallower from the surface of a substrate than currently available depth.
Thus, a structure is proposed that an epitaxially growth silicon layer is formed on a source/drain region to elevate the source/drain region from an original position of a substrate surface, thereby both making the junction depth from the substrate surface shallower and securing practical junction depth of the source/drain region. Such a structure is called an elevated source/drain structure (ESD structure) (see JP 03-049259A).
Meanwhile, since transistors in the memory cell region are formed much finer and denser than transistors in the peripheral circuit region, a gate length and also a gate distance become shorter, so that there is a need to make a junction shallower for restricting the short channel effect and ensuring low leak current.
There is a tendency that as the cell size decreases, a contact size and junction depth decrease, so that it is difficult to secure an electrical characteristic of a device, particularly to make the contact resistance lower. To solve this problem, JP 2003-338542A proposed a landing plug structure in which a single crystal silicon layer is epitaxially grown on a semiconductor substrate, and a polysilicon plug is formed thereon. The epitaxially growth silicon layer is also called a landing pad. With the formation of the landing pad, the contact resistance occurring due to natural oxide on the substrate surface is restricted from increasing.
Further, JP 2008-130756A discloses a semiconductor device such as a DRAM, in which a first epitaxial semiconductor layer on source/drain of a MOS transistor in a memory cell region, and a second epitaxial semiconductor layer on source/drain of a MOS transistor in a peripheral circuit region are formed.
However, in terms of process-simplification in the manufacture of the DRAM, it is generally carried out that the cell transistor and the peripheral circuit transistor are manufactured in common. When attempting to form transistors in the memory cell region and the peripheral circuit region using a common process, as described in JP 2008-130756A, before a high density impurity diffusion layer is formed in a peripheral circuit region, i.e. before an interlayer insulating film is formed on a semiconductor substrate, a semiconductor layer that serves as elevated source/drain in the peripheral circuit region and also serves as a landing pad in the memory cell region is formed.
Here, the ESD structure formed in the peripheral circuit region will be described with reference to FIGS. 8-10. Meanwhile, the figures are drawn by the inventors for explanation of a problem to be solved, so they are not the related art itself.
As shown in FIG. 8, shallow trench isolation (STI) 2 is formed in semiconductor substrate 1 to define an active area. Conductive material 4 and cap layer 5 are formed in the active area with gate insulating layer 3 interposed therebetween, and are patterned to form gate electrode 6. Next, sidewall spacer 8 formed of an insulating material is formed on a sidewall of the gate electrode, and impurity ions having reverse conductive type of semiconductor substrate 1, e.g. if semiconductor substrate 1 is p-type silicon, low concentration n-type impurity ions, are doped using the sidewall spacer 8 as a mask, to form LDD layer (low density impurity diffusion layer) 7. Semiconductor layer 10 is formed on LDD layer 7 by means of selective epitaxial growth.
In the selective epitaxial growth, it is known that since an outer side (end) of the formed semiconductor layer is surrounded by STI 2 formed from silicon oxide layer, the epitaxial silicon layer is restricted from being grown in a lateral direction, forming a tapered profile called a facet.
FIG. 9 shows the portion indicated by “A” of FIG. 8 in a magnified scale. In FIG. 9, “F” denotes the facet. Impurities are ion-implanted into semiconductor substrate 1 through semiconductor layer 10, thereby forming high density impurity diffusion layer 11. Semiconductor layer 10 with impurities ion-implanted becomes elevated source/drain region 10′. Here, in the outside of the active area (near STI 2), the depth of high density impurity diffusion layer 11 from the surface of semiconductor substrate 1 becomes deeper than the depth in the other region, thereby form deep impurity region 11d, due to the effect of facet F. FIG. 10 shows the ESD structure after the formation of high density impurity diffusion layer 11.
FIG. 11 shows a plan view of a transistor, wherein an active area comparted by STI 2 is indicated by “K”. High density impurity diffusion layer 11 is formed at deep impurity region 11d along the outer end of active area K. Thus, in region B adjacent to gate electrode 6, the source/drain electrode is formed by deep impurity region 11d, so that the short channel effect is ready to occur, making it difficult to obtain prescribed electric characteristics.
Meanwhile, in order to reduce the effect by the facet, it is considered that the epitaxially growth silicon layer is made thicker so as to make shallower the implantation depth in the semiconductor substrate. Further, since the facet is created at a contact surface between the epitaxially growth silicon layer and the silicon oxide layer to restrict the epitaxially growth silicon layer from being grown, there was a proposal to form the surface of the STI with a silicon nitride layer that does not restrict the epitaxially growth silicon layer from being grown, thereby preventing the formation of the facet. However, when attempting to form the epitaxially growth silicon layer on the source/drain electrode of the cell transistor using the same process, adjacent epitaxially growth silicon layers may contact each other to cause a short because the width of the STI separating the adjacent cell transistors from each other is narrower than the peripheral circuit region. This is because the epitaxial growth is carried out in a lateral direction. For example, this is because as the epitaxially growth silicon layer is made thicker, lateral projection also increases, and in addition, because in case that the silicon nitride layer hardly causing a facet is formed on the surface of the STI, lateral growth occurs in the same degree as the thickness of the epitaxially growth layer.